Erick Cook

519 Kingwood Dr NW                                                    (503) 585-8113

Salem, OR 97304                                                erick@fastFPGA.com

 

 

EDUCATION

 

Graduated from Oregon State University in 1982 with a degree in Engineering Physics.  Class work emphasized electrical engineering, physics, and math.

 

 

EMPLOYMENT

 

Independent Contractor                                            3/96 – Present

Erick M. Cook Engineering Services, Inc.

 

Co-architect and designer of the Image Acquisition system for the Electroglas Inspection Products “Quicksilver” wafer inspection system.  This design featured a Xilinx XC2V3000 FPGA, 4Gbytes of SDRAM, PCI bus interface, and TDI Camera interface.  My design responsibilities included the local bus interface which communicated with a PLX 9054 PCI Interface; a custom Die Image Creation module that constructed individual die images from the Camera input (at a clock rate of 106MHz); and a custom Image Subtraction & Manipulation machine capable of handling up to 400M pixels/sec.  This design work was done in VHDL.

 

Designer of several Logic Innovations, Inc., Intellectual Property products.  These synthesizable “cores” were available in both VHDL and Verilog.  They include the “Transmission Convergence Cell Inlet” – an ATM cell de-serializer; the “Transmission Convergence Cell Outlet” – an ATM cell serializer; the “UTOPIA Level II Interface Building Block”; and several revisions of the “PCI Bus Master / Target” and “PCI Bus Target” bus interfaces.  All products included Specification / Theory of Operation, synthesizable source code, and simulation test bench.

 

Co-designer of the “Multiport Queuer” – a custom product designed for Ariel Corp.  This device received a stream of ATM cells, separated the cells into a set of individual queues, and output from each queue on a prioritized basis to a multi-PHY UTOPIA Level II Transmit interface.  This design was done in Verilog.

 

 

Gerlitz Amplification, Inc.                                          4/97 – Present

 

Designer of the “Revelator Dual Amp” electric guitar amplifier.  This patented design incorporates two historic vacuum-tube amplifiers, a unique blending circuit, and a stereo power amplifier.  This product was reviewed by Guitar Player magazine, and is in use by a variety of musicians.

 

 

Logic Innovations, Inc.                                             3/86-3/96

 

Vice President and co-founder of Logic Innovations, Inc., an electronics design and consulting firm that employed more than 30 people.  When I departed in 1996, Logic Innovations was a multi-million dollar per year business.  While at Logic Innovations, I was directly responsible for: attending and making sales calls; providing technical, cost and schedule input for project quotations; designing system architecture and specification development; detailed electronic design, documentation, and prototype debug of numerous projects; prototype quantity manufacturing management; project and program management; other business related responsibilities.  This position also involved significant personal financial risk.

 

While at Logic Innovations I was personally responsible for the implementation of a variety of products, a few of which are highlighted below:

• The analog data acquisition sub-system for the Nellcore Puritan-Bennett 7250 Metabolic Monitor featuring a 12-bit precision multi-channel ADC quiet within 1 LSB.

• RF modems and DC power supplies for the General Instrument PCLinx cable TV modem.  This design used a 64-QAM high-speed demodulator, and a custom QPSK burst modulator.  The upstream QPSK modulator was 20 dB quieter than expected because of improved circuit board layout.

• PCI based data storage and retrieval system used to store large MPEG-II data streams.  This product was the predecessor to the Logic Innovations “Data Stream Transport System”, and also formed the basis for the Logic Innovations PCI “core” IP products.  This project, written in VHDL, was the first PCI design ever developed on the Lucent Technologies FPGA’s.

• 640 MHz ECLiPS ECL design for a Teledyne-Ryan optical “fly by wire” system.

• The Brooktree Bt81295 Personal Media Adapter.  This ASIC based design controlled data flow from a Bt812 video decoder through local DRAM frame buffer, to a Bt885 RamDAC and included an ISA bus interface.  It also included an FPGA based ASIC emulator.

• LaserJet printer made by Pacific Data Products.  Over $100 Million dollars of this product were sold.

• The power distribution system for the InFlight Phone Corp commercial aircraft telephone and data services system.  This system was installed in every seatback of several of American Airlines Boeing 757 aircraft.  Also responsible for debug assistance, and project management of this program.

 

Scientific Computer Systems                                   8/84 – 2/86

 

Designer of the Scalar Control Unit in the SCS-40, a Cray X/MP op-code compatible “mini-supercomputer”.  This 450 IC design was implemented entirely in 10KH ECL.  This board was responsible for performing instruction decode; maintaining the reservation status and controlling operand reads from the Address/Scalar register set; controlling the Scalar Linking mechanism; and maintaining the current CPU Exchange package.  Two US patents were issued relative to this design.

 

 

Syte Information Technology                                   2/84 – 7/84

 

Designer of a 2 Mbyte memory board (using 64 K DRAM).  This board featured a split transaction bus interface with a four request input queue; a full ECC subsystem which automatically wrote corrected data back into the memory array; a short burst mode using “Nibble Mode” DRAM; a page frame table with time stamp; a full diagnostic subsystem; capability for performing partial writes, Test&Set; and transparent refresh.

 

 

Intel Corporation                                                        6/82 – 1/84

 

Evaluation Engineer in the Development Systems group.  I was responsible for design review, and full product testing on the I2ICE 8086/8087 part probe, and EMV-50 in-circuit emulators.

 

Performed statistical process control research in the Manufacturing Yield Analysis group associated with Wafer Fab 4 in Aloha Oregon.  Performed lab experiments and data collection using a technique known as “sequential processing” to quantify the variance in electrical characteristics and product yield versus wafer position during manufacture.